Characterization and Evaluation of Hardware Loop Unrolling

General purpose programs contain loops that cannot be optimized by a compiler. When the body of a loop contains conditional control flow instructions or if the loop is controlled by a non-constant induction variable, the compiler again cannot unroll this loop. We have found that the compiler cannot unroll greater than 40-50% of the static loops in the set of programs studied. To be able to optimize the execution these loops, we have to detect loop behavior at runtime. We propose that loops that cannot be optimized by the compiler should be detected and unrolled using a hardware-based unrolling mechanism. Our design exploits the temporal locality found in loops to provide a higher degree of instruction level parallelism. Using hardware-based unrolling, multiple basic blocks can be retrieved from a dedicated loop cache, reducing the number of instruction cache and memory requests, while providing a large window of instructions for speculative execution. Before designing our hardware mechanism, we characterized all loops that cannot be optimized by the compiler. Using these characteristics we construct the design of a hardware mechanism that will allow us to unroll loop iterations dynamically. To drive our prediction mechanism, we use correlation between the pattern of branch outcomes that lead up to a loop with the path of branches executed within the loop body. We capture a history of the sequence of paths followed in a loop to predict the entire loop visit. We can then unroll entire loop bodies without the aid of the compiler. To characterize loop execution and evaluate the effectiveness of the proposed mechanisms, we study three different sets of benchmarks: mediabench, mibench and a subset of SPECint2000 (the loop intensive benchmarks). Our results show that hardware-based loop unrolling can be performed dynamically and provides us with new levels of instruction-level parallelism. We have found that we can consistently increase the IPC using this mechanism, achieving maximum speedups greater than 20%.